PyRTL AXI Library

Basic hardware implementation of AXI protocol subordinates, in the PyRTL hardware description language.

These subordinates can be useful for integrating pyrtlnet’s hardware with other systems, for example most Xilinx IP connects via AXI. The pyrtl_inference demo uses these subordinates when its --axi option is enabled.

See the pyrtl_axi demo for a simple example of how these subordinates work.

pyrtlnet.pyrtl_axi.make_axi_lite_subordinate(num_registers, num_writable_registers=None, channel=0)[source]

Makes a basic Register-based AXI-Lite subordinate.

This creates a set of Registers that can be read or written via AXI-Lite. Each register has a fixed bitwidth of 32 bits. The registers are assigned AXI addresses, which are byte addresses, so register 0 has AXI address 0, register 1 has AXI address 4, register 2 has AXI address 8, and so on.

See the AXI Specification for details.

The generated reset logic only resets Registers that can be written via AXI. See the num_writable_registers argument.

Parameters:

  • num_registers (int) – The number of Registers managed by this AXI-Lite subordinate. num_registers must be greater than zero. This many Registers will be created and returned by make_axi_lite_subordinate. Each Register is 32 bits wide. AXI addresses are byte addresses, so the Registers will be assigned AXI addresses 0, 4, 8, 12, …

  • num_writable_registers (int | None, default: None) – Determines which Registers may be written via AXI. If None, all Registers may be written via AXI. If not None, only the first num_writable_registers Registers may be written via AXI. Attempts to write a non-writable register will be ignored. num_writable_registers must be less than or equal to num_registers.

  • channel (int, default: 0) – Channel number for this AXI connection. Channel numbers are only used to name wires. When a module has multiple AXI interfaces, each AXI interface must use a different channel number to avoid wire name collisions.

Return type:

list[Register]

Returns:

A list of 32-bit Registers that can be read or written via AXI-Lite. These Registers can be freely read outside of this function. Any unwritable Registers (see the num_writable_registers argument) must have their next attribute set outside of this function.

pyrtlnet.pyrtl_axi.make_axi_stream_subordinate(mem, channel=0)[source]

Makes a basic MemBlock-based AXI-Stream subordinate.

The Stream’s data will be written to the MemBlock. The MemBlock will be completely overwritten with the Stream’s data, starting from address 0. The MemBlock’s addrwidth determines the number of data items to write, and the MemBlock’s bitwidth determines the size of each data item.

See the AXI-Stream Spec for details.

The generated reset logic does not reset the MemBlock’s contents.

Parameters:

  • mem (MemBlock) – The MemBlock to fill with the Stream’s data. The MemBlock’s bitwidth must be an even multiple of 8.

  • channel (int, default: 0) – Channel number for this AXI connection. Channel numbers are only used to name wires. When a module has multiple AXI interfaces, each AXI interface must use a different channel number to avoid wire name collisions.

Return type:

WireVector

Returns:

A 1-bit WireVector that indicates when loading is complete, and mem has been completely overwritten with Stream data.

pyrtlnet.pyrtl_axi.simulate_axi_lite_read(sim, provided_inputs, address, channel=0)[source]

Simulate reading an AXI-Lite register.

Parameters:

  • sim (Simulation) – The PyRTL Simulation to read the AXI-Lite register from.

  • provided_inputs (dict) – Additional Input values for the PyRTL Simulation.

  • address (int) – Address of the AXI-Lite register to read. AXI-Lite addresses are byte addresses, and each register is 32 bits wide, so address must be an even multiple of 4.

  • channel (int, default: 0) – Channel number for this AXI connection. Channel numbers are only used to name wires. When a module has multiple AXI interfaces, each AXI interface must use a different channel number to avoid wire name collisions.

Returns:

The contents of the requested AXI-Lite register.

pyrtlnet.pyrtl_axi.simulate_axi_stream_send(sim, provided_inputs, stream_data, channel=0)[source]

Simulate sending data to an AXI-Stream.

Parameters:

  • sim (Simulation) – The PyRTL Simulation to read the AXI-Lite register from.

  • provided_inputs (dict) – Additional Input values for the PyRTL Simulation.

  • stream_data (list[int]) – Data to send to the AXI-Stream. At most one element from this list will be sent each cycle. Each list element must fit in the stream’s bitwidth.

  • channel (int, default: 0) – Channel number for this AXI connection. Channel numbers are only used to name wires. When a module has multiple AXI interfaces, each AXI interface must use a different channel number to avoid wire name collisions.